Opportunities · Internship · Summer 2027

Physical Design Engineer Intern, BS - Summer 2027

Marvell Technology

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Pay: about $10-$43/hr
When: Summer 2027
Where: Westborough, MA · Remote

Before you apply

Graduation: Currently enrolled in a Bachelor's Degree in Electrical Engineering, Computer Engineering, or a related field with an expected graduation date between Fall 2027 – Summer 2028
Clearance: This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR).

What you'll do

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What they want

Completed courses focusing on VLSI, digital logic, circuit design, computer architecture, RTL synthesis, Verilog or SystemVerilog, place and route, static timing analysis, digital systems, or microelectronics
Proficiency in programming & scripting languages like Python, TCL, Perl, and Shell
Experience working in a Unix type environment
Experience using tools like Synopsys (PrimeTime), Cadence (Tempus), and Mentor
Strong analysis, problem solving, and communication skills
Expected Base Pay Range (USD)

About Marvell Technology

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Physical Design Engineer Intern, BS - Summer 2027

Marvell Technology

Westborough, MA

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Physical Design Engineer Intern, BS - Summer 2027

Marvell Technology

Westborough, MA

2 weeks ago

60 applicants

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About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

Marvell’s Physical Design teams span across multiple domains, giving you the opportunity to work on technologies that power next-generation cloud, AI, storage, and networking solutions. Some teams focus their design work on supporting architecture to GDSII (Graphic Data System) implementation of ASIC and processor designs. Other teams focus on timing analysis for future designs of our next-gen high-performance data center chips in a leading-edge CMOS process technology. Across all groups, you’ll collaborate with your direct team and cross-functional partners, working through technical design challenges to ensure we meet the performance, power, and area requirements of an active design.

What You Can Expect

Perform synthesis, floor planning, place and route, clock insertion, timing analysis, and timing closure on complex logic blocks using industry standard EDA tools (PrimeTime, Tempus)
Write scripts in Python, TCL, Perl, and Shell to aid design and development activities
Utilize problem solving skills to analyze, debug, and implement fixes for design violations using CAD tools
Collaborate with RTL, Synthesis, and other Design teams to resolve congestion & timing bottlenecks, and ensure that all designs converge & integrate in a timely manner

What We're Looking For

Currently enrolled in a Bachelor's Degree in Electrical Engineering, Computer Engineering, or a related field with an expected graduation date between Fall 2027 – Summer 2028
Completed courses focusing on VLSI, digital logic, circuit design, computer architecture, RTL synthesis, Verilog or SystemVerilog, place and route, static timing analysis, digital systems, or microelectronics
Proficiency in programming & scripting languages like Python, TCL, Perl, and Shell
Experience working in a Unix type environment
Experience using tools like Synopsys (PrimeTime), Cadence (Tempus), and Mentor
Strong analysis, problem solving, and communication skills

Expected Base Pay Range (USD)

29 - 57, $ per hour.

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

This role is eligible to participate in Marvell's bonus and equity plans, including a new hire equity grant and annual equity refreshers, ensuring you are rewarded for your contributions and remain invested in the company's long-term success.

Additional Compensation And Benefit Elements

Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights for our interns: medical, dental, and vision coverage, perks and discounts, robust mental health resources to prioritize emotional well-being, and paid holidays. Additional compensation may be available for intern PhD candidates. We look forward to sharing more with you during the interview process.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.

Interview Integrity

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

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Seniority level

Associate

Employment type

Internship

Industries

Semiconductor Manufacturing

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Posted

Sep 5, 2026

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