AI Accelerator Design Verification Intern

Get hands-on exposure to chip design and verification — perfect for EE/CompE students curious about how it all comes together.

What you'll do • Work with your mentor to develop verification plans for the accelerator • Write and debug SystemVerilog/UVM testbenches, checkers, and stimulus for your assigned block • Build tests, scoreboards, and reference models, and close functional and code coverage • Triage and root-cause failures with RTL designers, with mentorship from senior engineers • Participate in design and verification reviews and document your verification environment and results

Requirements • Working toward BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or related field • Recently completed coursework in digital design and verification, covering at least one of: computer microarchitecture; digital logic and RTL design; constrained-random and coverage-driven verification • Familiarity with verifying accelerator designs, such as: parallel datapaths and SIMD / SIMT / vector processing; numerical formats and computer arithmetic; data movement over DMA and memory interfaces • Hands-on SystemVerilog experience, including: testbench development (UVM preferred); assertions and functional coverage • Understanding of the end-to-end ASIC design flow and general VLSI concepts • Scripting experience (Python, Perl, or Tcl) for regression automation; C/C++ a plus