Design Architecture Engineer Intern

Back to jobs Design Architecture Engineer Intern San Jose, CA Apply Design Architecture Engineer Intern About the role Astera Labs is seeking a Design Architecture Engineer Intern to help define complex ASIC and system designs from product requirements through implementation.

You will work with architects and cross-functional engineering teams to develop clear architectural and microarchitectural specifications, evaluate design tradeoffs, and create the technical foundation for RTL, verification, physical design, DFT, and firmware.

You will gain hands-on experience turning system goals into block definitions, interfaces, dataflows, state machines, registers, clocking and reset behavior, performance budgets, and software-programming guidance.

You will own a scoped architecture project with mentorship and present the resulting analysis, specification, and recommendations. What you will do • Review product requirements, system use cases, protocol specifications, and technical constraints to identify architecture needs and open questions.

• Develop or update architectural specifications describing major blocks, functions, interfaces, clocking, resets, software interactions, and system behavior.

• Create or refine microarchitecture specifications for blocks and subsystems, including logical implementation, data structures, programmable registers, state machines, datapaths, and dataflow diagrams.

• Define and analyze interface behavior, ownership, ordering, buffering, flow control, error handling, interrupts, and recovery sequences. • Evaluate architecture tradeoffs involving latency, bandwidth, throughput, buffering, area, power, timing, scalability, complexity, and software impact.

• Build lightweight performance, capacity, traffic, or resource models using Python, spreadsheets, or comparable tools to support design decisions. • Review address maps, CSR/register definitions, configuration options, clock and reset relationships, and programming requirements for consistency and completeness.

• Trace requirements into implementation and verification considerations; identify assumptions, corner cases, and measurable acceptance criteria. • Participate in architecture, design, DV, physical-design, DFT, firmware, and program reviews; capture decisions, actions, risks, and unresolved items.

• Work with RTL, DV, PD, DFT, firmware, and systems engineers to clarify interfaces and improve the quality of handoff specifications. • Support architecture-to-RTL and architecture-to-DV handoff by organizing specifications, diagrams, register collateral, review evidence, and verification guidance.

• Document the completed project, technical rationale, tradeoffs, open questions, and recommendations; present the results to engineering stakeholders.

What you bring • Enrollment in a bachelor’s, master’s, or Ph.D. program in electrical engineering, computer engineering, computer science, or a related field.

• Coursework, research, or project experience in computer architecture, digital systems, ASIC/FPGA design, embedded systems, high-speed interfaces, or hardware/software integration.

• Understanding of digital design concepts such as datapaths, state machines, registers, memory systems, interrupts, clocks, resets, and interfaces. • Programming, scripting, or modeling experience with Python, C, C++, SystemVerilog, spreadsheets, or a comparable toolset.

• Ability to read technical specifications, organize complex information, reason about tradeoffs, and communicate precise technical decisions. • Familiarity with Linux development environments, Git, technical documentation, diagrams, and collaborative review workflows.

• Strong ownership, curiosity, practical judgment, and willingness to collaborate across engineering functions. Preferred qualifications • Experience writing architecture, microarchitecture, design, interface, protocol, or software-programming specifications.

• Familiarity with PCIe, CXL, UCIe, Ethernet, SerDes, chiplet, memory, or other high-speed interconnect architectures. • Experience with performance modeling, bandwidth/latency analysis, traffic modeling, queue or buffer sizing, or resource budgeting.

• Exposure to RTL, design verification, formal methods, physical design, DFT, firmware, or system bring-up workflows. • Familiarity with CSR and register-map design, address decoding, interrupt architecture, error reporting, telemetry, or debug infrastructure.

• Experience creating block diagrams, state diagrams, timing diagrams, interface tables, or traceability matrices. Internship experience and compensation This is a paid, hourly U.

S. internship. The applicable hourly rate is determined as part of the offer process and specified in the offer letter, depending on education level ranges form $35/hour to $55/hour.

U.S. interns currently receive a $500-per-week housing/relocation stipend for the duration of the internship. Interns participate in Early Career programming, including technical and professional-development sessions, community events, and an end-of-program project presentation.

Equal opportunity Astera Labs is an equal opportunity employer committed to fostering a diverse and inclusive workplace. We encourage anyone with relevant experience to apply.